IP SERVO MOTOR Cores for APA Actel
This IP permits to implement a PID controller (Proportional-Derivative-Integrative) for DC motors. The feedback position signal is acquired by optical encoder.

IP FMCW Cores for APA Actel
The following set of IPs permits to implement in a single APA (Actel) FPGA chip the signal processing required to implement an imaging radar system with continuous sample rate up to 64 Ksps.

IP FMCW Cores for STRATIX Altera
The following set of IPs permits to implement in a single STRATIX II (Altera) FPGA chip the signal processing required to implement an imaging radar system with continuous sample rate up to 100 Msps.

IP 32/64/128K Stream FFT Cores for STRATIX Altera
The "128K FFT Streaming IP" implements the Windowing and the FFT of complex arrays of 128K samples. An input stream of complex samples is delivered to the board through a Gigabit Ethernet (UDP). The stream can be processed in blocks of 32K (or 64K or 128K) by windowing and FFT. The results (block floating point) are delivered from the board on the Gigabit Ethernet.

IP 32/64/128K Stream FFT Cores DEMO
The "128K FFT Streaming IP Demonstraton" is a demo application project embedding the "128K FFT Streaming IP" to demonstrate its functionalities. The provided demo firmware is ready to be installed and run on an Altera evaluation board (NIOS Stratix II S180) equipped with an Ethernet Gigabit PHY board.

IP Video Cores for STRATIX Altera
The following set of IPs permits to implement in a single STRATIX II (Altera) FPGA chip the signal processing required to implement the extraction of a set of image features from a video stream of 25 frames per second.